1. Field of the Invention
The present invention relates to a semiconductor device, especially to a semiconductor device having a cross-wiring portion in which wirings cross each other.
2. Description of Related Art
When a transistor and an integrated circuit including the transistor operate in a frequency band higher than 10 GHz, it is necessary to reduce a parasitic capacitance around a gate electrode as much as possible in order to ensure a desired performance such as a characteristic or gain in the transistor.
In the transistor used in the high frequency band as described above, especially a transistor using a compound semiconductor device such as GaAs, an oxide film and a nitride film are formed as protective films to stabilize the operation of the transistor. However, the protective films such as the oxide film and the nitride film are required to have a thickness equal to or less than 0.2 um to reduce the parasitic capacitance, and an interlayer film is generally not applied. In the transistor and the integrated circuit as describe above, a technique is widely used in which a cross-wiring portion is not supported by the interlayer film and wirings are separated with an air interposed therebetween. This structure is called an air-bridge structure.
The air-bridge structure has a problem in that an upper layered wiring is deformed due to a thermal stress, mechanical vibration between the wiring layers, and an external force applied to the wiring structure during manufacturing processes, thereby contacting with a lover layered wiring. Japanese Unexamined Patent Application Publication Nos. 11-186381 and 10-12722 disclose a semiconductor device having a structure which prevents the wirings from contacting with each other due to deformation of an upper layered wiring.
FIG. 9 is a diagram showing a configuration of the semiconductor device disclosed in Japanese Unexamined Patent Application Publication No. 11-186381. In the semiconductor device disclosed in Japanese Unexamined Patent Application Publication No. 11-186381, a lower layered wiring 71 extending in the longitudinal direction of the drawing sheet is formed on a semiconductor substrate 70. An upper layered wiring 74 crossing the lower layered wiring 71 is formed to straddle the lower layered wiring 71 with a space 73 interposed therebetween. Further, a supporting column 72 of an insulator film is formed on the lower layered wiring 71 to prevent a short from occurring due to a contact between the upper layered wiring 74 and the lower layered wiring 71.
However, in the semiconductor device disclosed in Japanese Unexamined Patent Application Publication No. 11-186381, the supporting column 72 partially supports the upper and lower layered wirings but it is insufficient to prevent a short from occurring. Specifically, a wafer surface comes into contact with the supporting column 72 in a polishing process for a rear surface and a pelletizing process executed after the air-bridge structure is formed. When an external force is applied to the semiconductor device in the above processes, the upper layered wiring 74 positioned in an area where the supporting column 72 is not formed is pressed, thereby occasionally causing a short due to the contact between the upper layered wiring 74 and the lower layered wiring 71.
Further, even if the short does not occur, a capacitance between the wirings becomes larger, thereby causing a phase of the transistor to deviate from the designed phase when the distance between the wirings is reduced to around 0.1 um. Therefore, a phase matching condition in the design stage cannot be satisfied. Further, because an amount of deformation of the upper layered wiring caused by the above factors varies to a large extent, an amount of change of the phase also varies to a large extent. As a result, a desired performance cannot be obtained and the yield of a product decreases.
On the other hand, as shown in FIG. 10 Japanese Unexamined Patent Application Publication No. 10-12722 discloses a technique in which an insulator film 75 with a large thickness is formed on the lower layered wiring 71 to ensure a distance between the wirings, and an insulator film 76 with a small thickness is formed on the lower layered wiring 71 and the semiconductor substrate 70 to prevent the short from occurring due to the contact between the upper layered wiring 74 and the lower layered wiring 71.